Bug ID 2488981: FPGA datapath issue allows packets to be sent from host to network out of order

Last Modified: Oct 19, 2026

Affected Product(s):
F5OS F5OS-C(all modules)

Fixed In:
F5OS-C 1.8.2-HR3, F5OS v2.0.0-HR3

Opened: Aug 27, 2026

Severity: 2-Critical

Symptoms

Packets from the host to network are received out of order on BX520 blade.

Impact

Specific impact to UDP packet flows. UDP packets out of order can cause quality of service issues in audio and video streams.

Conditions

This typically happens in higher congestion or burst traffic conditions. The min/max packet size mix shows this issue most often, but packets out of order do happen with other random packet size mixes.

Workaround

Workaround requires a software update that contains an FPGA bitfile update to fix the issue.

Fix Information

The issue is in the Transmit Routing Engine (TRE) in the FPGA transmit datapath from host to network. Part of the TRE architecture splits the transmit datapath into 2 100G packet paths, each directed at a 100G MAC interface. The issue is in how the packet paths were split. The datapath architecture uses a tuple hash to ensure that all packets from a specific packet flow are directed down the same packet path. In this case, the hash was not applied correctly which allowed packets from a specific flow to run down both 100G datapaths, which creates a race condition. In lower congestion applications, the packets hold their order. In higher congestion or bursty applications with varying packet sizes, the packets can be received out of order.

Behavior Change

Guides & references

K10134038: F5 Bug Tracker Filter Names and Tips