Last Modified: Jul 30, 2025
Affected Product(s):
F5OS Velos
Known Affected Versions:
F5OS-A 1.8.0
Opened: May 02, 2025 Severity: 3-Major
For front panel LAGs on rSeries which span FPGAs (1.0/11.0, 2.0/12.0, etc) infrequent traffic which is not evenly distributed across the LAG members can lead to premature aging of L2 entries.
Missing L2 entries can cause excessive DLFs until the MAC address is re-learned.
- r10000 or r12000-series appliance - LAG members spanning FPGAs and minimal incoming traffic on the LAG can cause premature aging of L2 entries when the traffic isn't evenly distributed among LAG members.
Re-configure the LAG members such that they connect to the same FPGA (1.0/2.0, 11.0/12.0). Interfaces 1.0 through 10.0 are on one FPGA, and interfaces 11.0 through 20.0 are on the other FPGA.
None