Last Modified: Jul 28, 2026
Affected Product(s):
F5OS F5OS, F5OS-A, F5OS-C
Known Affected Versions:
F5OS v2.0.0, F5OS v2.0.0-HR1
Opened: Jun 15, 2026 Severity: 1-Blocking
RRDAG uses a protocol CAM to identify packet metadata to "hash" in Round Robin mode. A new RR-DAG feature added the capability for the packet metadata hash to match on L4 DPort in the Protocol CAM. There is an issue in the FPGA feature implementation of both sDAG and eDAG where the L4 DPort presented to the Protocol CAM is forced to zero if the packet had DPort=SPort. Because of the bug, packets would use the wrong disaggregation hash when the DPort=SPort since it wouldn't match the CAM entry.
Packets sent to the wrong CPU service destination. RR-DAG packet distribution is unbalanced.
Running RR-DAG and L4 source port == destination port.
This issue an FPGA feature implementation defect. Fix requires a SW update with new FPGA bitfiles.
None