Last Modified: Oct 06, 2020
See more info
Known Affected Versions:
11.4.1, 11.5.0, 11.5.1, 11.5.1 HF1, 11.5.1 HF10, 11.5.1 HF11, 11.5.1 HF2, 11.5.1 HF3, 11.5.1 HF4, 11.5.1 HF5, 11.5.1 HF6, 11.5.1 HF7, 11.5.1 HF8, 11.5.1 HF9, 11.5.10, 11.6.0, 11.6.0 HF1, 11.6.0 HF2, 11.6.0 HF3, 11.6.0 HF4
12.0.0, 11.6.0 HF5, 11.5.2, 11.4.1 HF9
Opened: Aug 15, 2014
Related AskF5 Article: K16171
HTTP caching configured in a Web Acceleration profile may dispatch internal messages out-of-order, leading to assert
Due to this rarely occurring race condition, a tmm_panic occurs ('valid pcb') when a connection is being closed and the ramcache feature is able fulfill an incoming request. Standby unit becomes temporarily unavailable.
Assert may occur when the following conditions are met: - Virtual server has HTTP caching configured in a Web Acceleration profile. - Virtual server has mirroring enabled. - Device is in standby mode. - Active unit is unable to fulfill incoming HTTP request (ramcache entry is invalid / no pool members). - Standby unit is able to fulfill mirrored request (ramcache entry is valid).
Do not use connection mirroring when HTTP caching is configured in a Web Acceleration.
HTTP caching configured in a Web Acceleration profile no longer dispatches internal messages out-of-order, leading to assert.